The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for wide bandwidth resonant global clock distribution.
In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. The clock distribution network distributes the clock signal from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention is given to the characteristics of clock signals and the electrical networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.
Clock signals are typically loaded with the greatest fanout and operate at the highest speeds of any signal, either control or data, within the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling in that long global interconnect lines become significantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register.
The clock distribution network often takes a significant fraction of the power consumed by a chip. Resonant clock distribution can save up to 50% of the global clock power. Modern processors operate over a frequency range wider than the bandwidth of a resonant circuit. Also, quickly switching between resonant and non-resonant clock modes cases unacceptable changes to the clock waveform. Resonant clocking takes significant inductance; however, typical planar, spiral inductors cause too much disruption to the power supply grid and higher level routing. Resonant or other multi-mode clocking changes the required driving strength of the sector buffers resulting in changes in slew rate, changes in driver latency, and short cycles during stepping from one mode to another, especially to resonant clock mode.
Different sectors of the grid are loaded differently so a single buffer size is not optimal. Clock grid tuning is adjusted last minute, and sector loads can change requiring buffer adjustment, often after front end-of-line (FEOL), which comprises the steps taken to form transistors, anything below the metal layer.